Indexed by:Journal paper First Author:Tao Wu Correspondence Author:Xingsheng Wang Co-author: Haowen Luo, Xingsheng Wang,Asen Asenov, Xiangshui Miao Journal:IEEE Transactions on Electron Devices Included Journals:EI、SCI Affiliation of Author(s):Huazhong University of Science and Technology Place of Publication:USA Discipline:Engineering First-Level Discipline:Electronic Science And Technology Document Type:J Volume:67 Issue:6 Page Number:2255-2262 Key Words:Compact model, FinFETs, parasitic resistance, scaling, TCAD Date of Publication:2020-06-01 Abstract:Due to the increasing importance and complexity of source/drain parasitic resistance (Rsd) in nanoscale CMOS technology and circuit design, a predictive 3-D structure-aware Rsd compact model is developed and comprehensively validated in respect of 7-nm bulk FinFET TCAD platform. Our TCAD model was calibrated againstGlobalFoundries/Samsung 7-nmFinFETtechnology experimental data and further validated by 2-D Poisson– Schrodinger simulation. Verilog-A coded SPICE Rsd compactmodel,coupledwithpropertransportmodels,indicates that the degradation of saturation current as well as the proportion of Rsd