Nano-Scale CMOS Analog Circuits : Models and CAD Techniques for High-Level Design

[BOOK DESCRIPTION]

Reliability concerns and the limitations of process technology can sometimes restrict the innovation process involved in designing nano-scale analog circuits. The success of nano-scale analog circuit design requires repeat experimentation, correct analysis of the device physics, process technology, and adequate use of the knowledge database. Starting with the basics, Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design introduces the essential fundamental concepts for designing analog circuits with optimal performances. This book explains the links between the physics and technology of scaled MOS transistors and the design and simulation of nano-scale analog circuits. It also explores the development of structured computer-aided design (CAD) techniques for architecture-level and circuit-level design of analog circuits. The book outlines the general trends of technology scaling with respect to device geometry, process parameters, and supply voltage. It describes models and optimization techniques, as well as the compact modeling of scaled MOS transistors for VLSI circuit simulation.* Includes two learning-based methods: the artificial neural network (ANN) and the least-squares support vector machine (LS-SVM) method * Provides case studies demonstrating the practical use of these two methods * Explores circuit sizing and specification translation tasks * Introduces the particle swarm optimization technique and provides examples of sizing analog circuits * Discusses the advanced effects of scaled MOS transistors like narrow width effects, and vertical and lateral channel engineering Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design describes the models and CAD techniques, explores the physics of MOS transistors, and considers the design challenges involving statistical variations of process technology parameters and reliability constraints related to circuit design.

[TABLE OF CONTENTS]

List of Figures                                    xv
List of Tables                                     xxi
Preface                                            xxiii
About the Authors                                  xxvii
1 Introduction                                     1    (34)
  1.1 Introduction                                 1    (1)
  1.2 Characterization of Technology Scaling       2    (12)
    1.2.1 Constant Field Scaling                   2    (1)
    1.2.2 Constant Voltage Scaling                 2    (2)
    1.2.3 Nonscaling Effects                       4    (1)
    1.2.4 Generalized Scaling and Technology       5    (9)
    Trends
      1.2.4.1 International Technology Roadmap     5    (1)
      for Semi-conductors
      1.2.4.2 Predictive Technology Modeling       6    (1)
      1.2.4.3 Scaling of Geometry Parameters       6    (2)
      1.2.4.4 Scaling of Channel Doping, Supply    8    (2)
      Voltage, and Threshold Voltage
      1.2.4.5 Scaling of Performances              10   (2)
      1.2.4.6 Scaling of Source-Drain              12   (2)
      Resistance and Saturation Velocity
  1.3 Analog Design Challenges in Scaled CMOS      14   (5)
  Technology
    1.3.1 Degradation of Output Resistance and     14   (1)
    Intrinsic Gain
    1.3.2 Gate Oxide Leakage Current               15   (1)
    1.3.3 Noise Performance                        16   (1)
    1.3.4 Analog Power Consumption                 16   (2)
    1.3.5 Drain Current Mismatch                   18   (1)
    1.3.6 Transition Frequency                     18   (1)
    1.3.7 Reliability Constraints                  18   (1)
  1.4 Motivation for CAD Techniques                19   (3)
    1.4.1 Design Productivity Gap                  19   (1)
    1.4.2 Design Creativity Gap                    20   (2)
  1.5 Conventional Design Techniques for Analog    22   (6)
  IC Design
    1.5.1 Bottom-Up Design Technique               22   (2)
      1.5.1.1 Advantages and Limitations           24   (1)
    1.5.2 Top-Down Design Technique                24   (4)
      1.5.2.1 Abstraction Levels                   25   (1)
      1.5.2.2 Hierarchical Design Strategy         26   (1)
      1.5.2.3 Advantages and Limitations           26   (2)
  1.6 Knowledge-Based CAD Technique for Analog     28   (5)
  ICs
    1.6.1 Motivation for Knowledge Extraction      29   (1)
    and Management
    1.6.2 Problem Formulations                     29   (1)
    1.6.3 Outline of the Procedure                 30   (2)
      1.6.3.1 Numerical Simulation-Based           30   (2)
      Evaluation
      1.6.3.2 Analytical Model-Based Evaluation    32   (1)
    1.6.4 Salient Features                         32   (1)
  1.7 Summary and Conclusion                       33   (2)
2 High-Level Modeling and Design Techniques        35   (50)
  2.1 Introduction                                 35   (1)
  2.2 High-Level Model                             36   (3)
    2.2.1 Behavioral Models                        36   (1)
    2.2.2 Performance Models                       37   (1)
    2.2.3 Feasibility Models                       37   (1)
    2.2.4 Characteristics of Good High-Level       38   (1)
    Models
  2.3 Behavioral Model Generation Technique        39   (10)
    2.3.1 Manual Abstraction                       39   (2)
    2.3.2 Model Order Reduction Technique          41   (3)
      2.3.2.1 MOR, for LTI Systems                 41   (2)
      2.3.2.2 MOR, for LTV Systems                 43   (1)
      2.3.2.3 MOR, for Nonlinear Systems           43   (1)
    2.3.3 Symbolic Analysis Technique              44   (5)
      2.3.3.1 Basic Concepts                       44   (2)
      2.3.3.2 Methodology                          46   (1)
      2.3.3.3 Simplification of Expressions        47   (2)
  2.4 Introduction to Optimization Techniques      49   (7)
    2.4.1 Optimization Problem Formulation         49   (2)
    2.4.2 Optimality Criteria                      51   (1)
    2.4.3 Classification of Optimization           51   (3)
    Algorithms
      2.4.3.1 Single-Variable Optimization         51   (1)
      Algorithms
      2.4.3.2 Multi-Variable Optimization          51   (1)
      Algorithm
      2.4.3.3 Constrained Optimization             52   (1)
      Algorithms
      2.4.3.4 Specialized Optimization             53   (1)
      Algorithms
      2.4.3.5 Nontraditional Stochastic            53   (1)
      Optimization Algorithms
    2.4.4 Concept of Local Optima and Global       54   (1)
    Optima
    2.4.5 Characterization of Optimization         55   (1)
    Algorithms
  2.5 Some Important Optimization Algorithms       56   (5)
    2.5.1 Cauchy's and Newton's Steepest           56   (1)
    Descent Algorithm
    2.5.2 Genetic Algorithm                        57   (3)
    2.5.3 Simulated Annealing                      60   (1)
  2.6 Multi-Objective Optimization Method          61   (2)
    2.6.1 Pareto Optimal Front                     62   (1)
  2.7 Design Space Exploration                     63   (1)
  2.8 Computational Complexity of a CAD            63   (5)
  Algorithm
    2.8.1 Time and Space Complexity                64   (1)
    2.8.2 Asymptotic Notations                     65   (2)
      2.8.2.1 Big-Oh Notation O()                  65   (1)
      2.8.2.2 Omega Notation Ω()             66   (1)
      2.8.2.3 Theta Notation Θ()             66   (1)
    2.8.3 Categorization of CAD Problems           67   (1)
    2.8.4 Complexity Classes for CAD Problems      67   (1)
  2.9 Technology-Aware Computer Aided IC Design    68   (7)
  Technique
    2.9.1 Introduction to TCAD                     69   (1)
    2.9.2 Process Simulation through TCAD          70   (1)
    2.9.3 Device Simulation through TCAD           70   (1)
    2.9.4 Design for Manufacturability and Yield   71   (2)
    2.9.5 Process Compact Model Development        73   (2)
    through TCAD
      2.9.5.1 Parameter Extraction Technique       74   (1)
    2.9.6 Design Techniques for Nano-Scale         75   (1)
    Analog ICs
  2.10 Commercial Design Tools                     75   (9)
    2.10.1 IC Design                               75   (6)
      2.10.1.1 Cadenceｮ Virtuoso Analog Design     77   (2)
      Environment
      2.10.1.2 Synopsys Galaxy Custom Design       79   (1)
      2.10.1.3 Tanner EDA HiPer Siliconｮ           80   (1)
      2.10.1.4 Mentor Graphics Pyxisｮ Suite        81   (1)
    2.10.2 TCAD                                    81   (5)
      2.10.2.1 Silvaco Tool Suite                  81   (2)
      2.10.2.2 Synopsys Device Simulation Tool     83   (1)
      Suite
  2.11 Summary and Conclusion                      84   (1)
3 Modeling of Scaled MOS Transistor for VLSI       85   (72)
Circuit Simulation
  3.1 Introduction                                 85   (1)
  3.2 Device Modeling                              86   (1)
    3.2.1 Categories of Device Models              87   (1)
  3.3 Compact Models                               87   (2)
    3.3.1 Commercial Compact Models                88   (1)
  3.4 Long-Channel MOS Transistor                  89   (1)
  3.5 Threshold Voltage Model for Long-Channel     90   (2)
  Transistor with Uniform Doping
    3.5.1 Body Effect                              91   (1)
  3.6 SPICE Level 1 Drain Current Model            92   (5)
    3.6.1 Channel Length Modulation Effect         96   (1)
  3.7 SPICE Level 3 I-V Model                      97   (2)
  3.8 MOSFET Capacitances                          99   (11)
    3.8.1 Characterization of Intrinsic            100  (4)
    Capacitances
      3.8.1.1 Charge Partitioning                  103  (1)
    3.8.2 Characterization of Extrinsic            104  (3)
    Capacitances
      3.8.2.1 Overlap and Fringing Capacitances    104  (1)
      3.8.2.2 Junction Capacitances                105  (2)
    3.9 Short-Channel MOS Transistor               107  (3)
  3.10 Threshold Voltage for Short-Channel MOS     110  (10)
  Transistor
    3.10.1 Source/Drain Charge Sharing             110  (2)
      3.10.1.1 Level 2 Compact Model for VT        111  (1)
    3.10.2 Drain-Induced Barrier Lowering          112  (2)
      3.10.2.1 Level 3 Model of DIBL               113  (1)
    3.10.3 BSIM3/BSIM4 Compact Model for           114  (3)
    Threshold Voltage
    3.10.4 Short-Channel Effect Immunity           117  (3)
  3.11 I-V Model for Short-Channel MOS             120  (8)
  Transistor
    3.11.1 Carrier Mobility Degradation            120  (3)
      3.11.1.1 Surface Mobility                    120  (1)
      3.11.1.2 Mobility Dependence on Gate Field   121  (2)
    3.11.2 Carrier Velocity Saturation             123  (1)
    3.11.3 Drain Current in Scaled MOS             124  (4)
    Transistor
  3.12 Weak Inversion Characteristics of a         128  (6)
  Scaled MOS Transistor
    3.12.1 Subthreshold Swing                      131  (3)
  3.13 Hot Carrier Effect                          134  (7)
    3.13.1 Spatial Distribution of Lateral         134  (3)
    Electric Field
    3.13.2 Substrate Current Due to Hot-Carrier    137  (2)
    Effects
    3.13.3 Gate Current Due to Hot-Carrier         139  (2)
    Effects: Lucky Electron Model
    3.13.4 Reduction of Drain Field through LDD    141  (1)
    Structure
  3.14 Source-Drain Resistance Model               141  (4)
    3.14.1 Compact Modeling                        143  (1)
    3.14.2 Salicide Technology                     144  (1)
  3.15 Physical Model for Output Resistance        145  (5)
    3.15.1 Compact Modeling                        147  (3)
  3.16 Poly-Silicon Gate Depletion Effect          150  (2)
    3.16.1 Electrical Oxide Thickness              152  (1)
    3.16.2 Reduction of Poly-Gate Depletion        152  (1)
  3.17 Effective Channel Length and Width          152  (4)
    3.17.1 Effective Channel Length                154  (6)
      3.17.1.1 Extraction of the Effective         155  (1)
      Channel Length
  3.18 Summary and Conclusion                      156  (1)
4 Performance and Feasibility Model Generation     157  (60)
Using Learning-Based Approach
  4.1 Introduction                                 157  (1)
  4.2 Requirement of Learning-Based Approaches     157  (1)
  4.3 Regression Problem for Performance Model     158  (1)
  Generation
  4.4 Some Related Works                           158  (2)
  4.5 Preliminaries on Artificial Neural Network   160  (4)
    4.5.1 Basic Components                         160  (1)
    4.5.2 Mathematical Model of Neuron             160  (1)
    4.5.3 MLP Feed-Forward NN Structure            161  (1)
    4.5.4 Feed-Forward Computation                 162  (1)
    4.5.5 Success of MLP NN Structures             163  (1)
    4.5.6 Network Size and Layers                  164  (1)
  4.6 Neural Network Model Development             164  (7)
    4.6.1 Formulation of Inputs and Outputs        164  (1)
    4.6.2 Data Range and Sample Distribution       164  (3)
    4.6.3 Data Collection                          167  (1)
    4.6.4 Data Organization and Data               167  (1)
    Preprocessing
    4.6.5 Neural Network Training                  168  (2)
    4.6.6 Quality Measures                         170  (1)
    4.6.7 Generalization Ability, Overlearning,    170  (1)
    and Underlearning
  4.7 Case Study 1: Performance Modeling of        171  (3)
  CMOS Inverter
  4.8 Case Study 2: Performance Modeling of        174  (8)
  Spiral Inductor
  4.9 Dynamic Adaptive Sampling                    182  (5)
    4.9.1 Motivation of the Algorithm              183  (1)
    4.9.2 Simple Dynamic Sampling Algorithms       183  (1)
    4.9.3 Dynamic Adaptive Sampling Algorithm      184  (2)
      4.9.3.1 Initial Sample Size                  184  (1)
      4.9.3.2 Sampling Schedule                    184  (1)
      4.9.3.3 Stopping Criteria                    185  (1)
    4.9.4 Demonstration with CMOS Inverter         186  (1)
    Problem
  4.10 Introduction to Least Squares Support       187  (11)
  Vector Machines
    4.10.1 Least-Squares Support Vector            187  (2)
    Regression
    4.10.2 Least-Squares Support Vector            189  (3)
    Classification
      4.10.2.1 Classifier Accuracy                 191  (1)
    4.10.3 Choice of Kernel Functions and          192  (9)
    Hyperparameter Tuning
      4.10.3.1 Grid Search Technique               194  (2)
      4.10.3.2 Genetic Algorithm-Based Technique   196  (2)
  4.11 Feasible Design Space and Feasibility       198  (3)
  Model
  4.12 Case Study 3: Combined Feasibility and      201  (3)
  Performance Modeling of Two-Stage Operational
  Amplifier
    4.12.1 Feasibility Model                       202  (1)
    4.12.2 Performance Model                       203  (1)
  4.13 Case Study 4: Architecture-Level            204  (4)
  Performance Modeling of Analog Systems
  4.14 Meet-in-the-Middle Approach for             208  (3)
  Construction of Architecture-Level Feasible
  Design Space
    4.14.1 Application Bounded Space Da            208  (2)
    4.14.2 Circuit Realizable Space Dc             210  (1)
    4.14.3 Feasible Design Space Identification    210  (1)
  4.15 Case Study 5: Construction of               211  (4)
  Feasibility Model at Architecture Level of an
  Interface Electronics for MEMS Capacitive
  Accelerometer System
  4.16 Summary and Conclusion                      215  (2)
5 Circuit Sizing and Specification Translation     217  (36)
  5.1 Introduction                                 217  (1)
  5.2 Circuit Sizing as a Design Space             217  (4)
  Exploration Problem
    5.2.1 Problem Formulations                     217  (2)
    5.2.2 Solution Techniques                      219  (1)
    5.2.3 Design Flow                              220  (1)
      5.2.3.1 Evaluation of Cost Functions         221  (1)
  5.3 Particle Swarm Optimization Algorithm        221  (5)
  (PSO)
    5.3.1 Dynamics of a Particle in PSO            222  (1)
    5.3.2 Flow of the Algorithm                    223  (1)
    5.3.3 Selection of Parameters for PSO          223  (14)
      5.3.3.1 Inertia Weight ω               225  (1)
      5.3.3.2 Maximum Velocity Vmax                225  (1)
      5.3.3.3 Swarm Size S                         225  (1)
      5.3.3.4 Acceleration Coefficient c1 and c2   225  (1)
  5.4 Case Study 1: Design of a Two-Stage          226  (3)
  Miller OTA
  5.5 Case Study 2: Synthesis of on-Chip Spiral    229  (5)
  Inductors
  5.6 Case Study 3: Design of a Nano-Scale CMOS    234  (3)
  Inverter for Symmetric Switching
  Characteristics
  5.7 The gm/ID Methodology for Low Power Design   237  (13)
    5.7.1 Study of the gm/ID and サ Parameters     238  (3)
    for Analog Design
    5.7.2 gm/ID Based Sizing Methodology           241  (5)
    5.7.3 Case Study 4: Sizing of Low-Power        246  (4)
    Nano-Scale Miller OTA Using the gm/ID
    Methodology
  5.8 High-Level Specification Translation         250  (1)
  5.9 Summary and Conclusion                       251  (2)
6 Advanced Effects of Scaled MOS Transistors       253  (52)
  6.1 Introduction                                 253  (1)
  6.2 Narrow Width Effect on Threshold Voltage     253  (4)
    6.2.1 LOCOS Isolated MOS Transistors           254  (1)
    6.2.2 Shallow Trench Isolated (STI) MOSFETs    255  (2)
  6.3 Channel Engineering of MOS Transistor        257  (6)
    6.3.1 Non-Uniform Vertical Doping              257  (4)
      6.3.1.1 High-to-Low Profile                  258  (2)
      6.3.1.2 Low-to-High Retrograde Profile       260  (1)
      6.3.1.3 Compact Modeling of Vertical         260  (1)
      Non-Uniform Doping Effect
    6.3.2 Pocket (Halo) Implantation               261  (2)
  6.4 Gate Leakage Current                         263  (12)
    6.4.1 Basic Ideas about Quantum Mechanical     263  (3)
    Tunneling
    6.4.2 Gate Oxide Tunneling Current             266  (3)
      6.4.2.1 Energy Band Theory Model             266  (1)
      6.4.2.2 Fowler-Nordheim Tunneling            266  (3)
      6.4.2.3 Direct Tunneling                     269  (1)
    6.4.3 Gate Leakage Mechanisms and Leakage      269  (3)
    Components for MOS Transistors
    6.4.4 Compact Modeling                         272  (1)
    6.4.5 Effects of Gate Leakage                  272  (3)
  6.5 High-κ Dielectrics and                 275  (4)
  Metal-Gate/High-κ CMOS Technology
    6.5.1 High-κ Dielectric Materials        275  (3)
    6.5.2 Metal Gate                               278  (1)
  6.6 Advanced Device Structures of MOS            279  (5)
  Transistors
    6.6.1 SOI MOS Transistor                       279  (1)
    6.6.2 Double Gate (DG)-MOS Transistors         280  (2)
    6.6.3 FinFETs                                  282  (2)
  6.7 Noise Characterization of MOS Transistors    284  (10)
    6.7.1 Fundamental Sources of Noise             284  (2)
    6.7.2 Characterization of Thermal Noise in     286  (2)
    MOS Transistors
    6.7.3 Characterization of Flicker Noise in     288  (6)
    MOS Transistors
      6.7.3.1 Physical Mechanism of Flicker        288  (3)
      Noise
      6.7.3.2 Physics-Based Modeling of Flicker    291  (3)
      Noise
  6.8 Gate Resistance and Substrate Network        294  (8)
  Model of MOS Transistor for RF Applications
    6.8.1 Parasitic Components of MOS              297  (1)
    Transistors
    6.8.2 Gate Resistance Modeling                 298  (3)
      6.8.2.1 Minimization of Gate Resistance      300  (1)
    6.8.3 Substrate Network Modeling               301  (1)
  6.9 Summary and Conclusion                       302  (3)
7 Process Variability and Reliability of           305  (46)
Nano-Scale CMOS Analog Circuits
  7.1 Introduction                                 305  (1)
  7.2 Basic Concepts on Yield and Reliability      306  (7)
    7.2.1 Yield                                    306  (2)
    7.2.2 Design Tolerance and Capability Index    308  (2)
    7.2.3 Reliability Bathtub Curve                310  (3)
  7.3 Sources of Variations in Nanometer Scale     313  (3)
  Technology
    7.3.1 Process Variations                       314  (2)
    7.3.2 Environmental Variations                 316  (1)
    7.3.3 Aging Variations or Reliability          316  (1)
  7.4 Systematic Process Variations                316  (4)
    7.4.1 Optical Proximity Correction             317  (1)
    7.4.2 Phase Shift Mask                         317  (1)
    7.4.3 Layout-Induced Strain                    318  (1)
    7.4.4 Well Proximity Effect                    319  (1)
  7.5 Random Process Variations                    320  (7)
    7.5.1 Random Discrete Dopants                  321  (1)
    7.5.2 Line Edge Roughness                      322  (5)
    7.5.3 Oxide Thickness Variations               327  (1)
    7.5.4 High-it Dielectric Morphology and        327  (1)
    Metal Gate Granularity
  7.6 Statistical Modeling                         327  (8)
    7.6.1 Worst Case Corner Analysis               329  (2)
    7.6.2 Monte Carlo Simulation Technique         331  (1)
    7.6.3 Statistical Corner Technique             331  (3)
    7.6.4 Mismatch in Analog Circuits              334  (1)
  7.7 Physical Phenomena Affecting the             335  (7)
  Reliability of Scaled MOS Transistor
    7.7.1 Time Dependent Dielectric Breakdown      337  (5)
    (TDDB)
      7.7.1.1 Electrostatics in Dielectrics        337  (1)
      7.7.1.2 Energy Band Theory of Dielectric     338  (1)
      Breakdown
      7.7.1.3 Anode Hole Injection Theory          339  (2)
      7.7.1.4 Percolation Theory                   341  (1)
      7.7.1.5 Statistics of Gate Oxide Breakdown   341  (1)
      7.7.1.6 Soft and Hard Breakdown              341  (1)
    7.7.2 Hot Carrier Injection (HCI)              342  (1)
    7.7.3 Negative Bias Temperature Instability    342  (1)
    (NBTI)
  7.8 Physical Model for MOSFET Degradation Due    342  (5)
  to HCI
    7.8.1 Physical Mechanism for Interface Trap    343  (4)
    Generation
      7.8.1.1 Physical Model                       344  (1)
      7.8.1.2 Application to Analog Circuit        345  (2)
      Design
  7.9 Reaction-Diffusion Model for NBTI            347  (1)
  7.10 Reliability Simulation for Analog           347  (2)
  Circuits
  7.11 Summary and Conclusion                      349  (2)
Bibliography                                       351  (18)
Index                                              369