Per Stenstr m教授讲座

主题：Efficient Statistical-based Cache Compression

时间：10月15日上午10:00 ~ 12:00

地点：电子与信息工程学院学术报告厅（西一楼339）

Per Stenstrom 是计算机系统结构方面著名专家，他是瑞典查尔姆斯理工大学教授，ACM/IEEE Fellow，瑞典皇家工程科学院院士、欧洲人文与科学院院士、西班牙皇家工程院院士。

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Efficient Statistical-based Cache Compression

Per Stenstrom
Chalmers University of Technology
Sweden

Low utilization of on-chip cache capacity limits performance and causes energy wastages because of the long latency, the limited bandwidth, and the energy consumption associated with off-chip memory accesses. Value replication the same value appears in multiple memory locations is an important source of low capacity utilization. While cache compression techniques in the past manage to code frequent values densely, they trade off a high compression ratio for low decompression latency, thus missing opportunities to utilize on-chip cache capacity more effectively.

This talk  presents, for the first time, a detailed design-space exploration of statistical-based cache compression. We show that more aggressive, statistical-based compression approaches, such as Huffman, that have been excluded in the past due to the processing overhead for compression and decompression, are prime candidates for cache and memory compression. We first find that the overhead of statistics acquisition to
generate new codewords is low because value locality varies little over time and across applications so new encodings need to be generated rarely making it possible to off-load it to software routines. We then show that the high compression ratio obtained by Huffman-based cache compression makes it possible to enjoy the performance benefits of 4X larger last-level caches at a power consumption that is about 50% lower than 4X times larger caches.

Bio:

Per Stenstrom is Professor of Comuter Engineering at Chalmers University of Technology. His research interests are in parallel computer architecture. He has authored or co-authored three textbooks and more than 130 international publications in this area. He has been program chairman of  the IEEE/ACM Symposium on Computer Architecture, the IEEE High-Performance Computer Architecture Symposium, and the IEEE Parallel and Distributed Processing Symposium and acts as Senior Associate Editor of ACM TACO and Associate Editor-in-Chief of JPDC. He is a Fellow of the ACM and the IEEE and a member of Academia Europaea, the Royal Swedish Academy of Engineering Sciences and the Royal Spanish Academy of Engineering Science.