RF Circuit Design

[BOOK DESCRIPTION]

This revised edition immerses practicing and aspiring industry professionals in the complex world of RF design. Completely restructured and reorganized with new content, end-of-chapter exercises, illustrations, and an appendix, the book presents integral information in three complete sections exploring RF and digital circuit design; the fundamentals of differential pair and common-mode rejection ratio (CMRR); low-noise amplifier (LNA), power amplifier (PA), voltage-controlled oscillator (VCO), mixers; and much more. It is an ideal book for engineers and managers who work in RF circuit design and for courses in electrical or electronic engineering.

[TABLE OF CONTENTS]

Preface To The Second Edition                      xix
Part I Design Technologies And Skills              1  (426)
  1 Difference Between RF And Digital Circuit      3  (12)
  Design
    1.1 Controversy                                3  (3)
      1.1.1 Impedance Matching                     4  (1)
      1.1.2 Key Parameter                          5  (1)
      1.1.3 Circuit Testing and Main Test          6  (1)
      Equipment
    1.2 Difference of RF and Digital Block in a    6  (3)
    Communication System
      1.2.1 Impedance                              6  (1)
      1.2.2 Current Drain                          7  (1)
      1.2.3 Location                               7  (2)
    1.3 Conclusions                                9  (1)
    1.4 Notes for High-Speed Digital Circuit       9  (1)
    Design
    Further Reading                                10 (1)
    Exercises                                      11 (1)
    Answers                                        11 (4)
  2 Reflection And Self-Interference               15 (46)
    2.1 Introduction                               15 (1)
    2.2 Voltage Delivered from a Source to a       16 (7)
    Load
      2.2.1 General Expression of Voltage          16 (4)
      Delivered from a Source to a Load when l
      << λ4 so that Td -> 0
      2.2.2 Additional Jitter or Distortion in     20 (3)
      a Digital Circuit Block
    2.3 Power Delivered from a Source to a Load    23 (10)
      2.3.1 General Expression of Power            23 (3)
      Delivered from a Source to a Load when l
      << λ/4 so that Td -> 0
      2.3.2 Power Instability                      26 (1)
      2.3.3 Additional Power Loss                  27 (1)
      2.3.4 Additional Distortion                  28 (3)
      2.3.5 Additional Interference                31 (2)
    2.4 Impedance Conjugate Matching               33 (9)
      2.4.1 Maximizing Power Transport             33 (2)
      2.4.2 Power Transport without Phase Shift    35 (2)
      2.4.3 Impedance Matching Network             37 (3)
      2.4.4 Necessity of Impedance Matching        40 (2)
    2.5 Additional Effect of Impedance Matching    42 (9)
      2.5.1 Voltage Pumped up by Means of          42 (7)
      Impedance Matching
      2.5.2 Power Measurement                      49 (2)
    Appendices                                     51 (7)
      2.A.1 VSWR and Other Reflection and          51 (7)
      Transmission Coefficients
      2.A.2 Relationships between Power (dBm),     58 (1)
      Voltage (V), and Power (W)
    Reference                                      58 (1)
    Further Reading                                58 (1)
    Exercises                                      59 (1)
    Answers                                        59 (2)
  3 Impedance Matching In The Narrow-Band Case     61 (70)
    3.1 Introduction                               61 (2)
    3.2 Impedance Matching by Means of Return      63 (5)
    Loss Adjustment
      3.2.1 Return Loss Circles on the Smith       63 (3)
      Chart
      3.2.2 Relationship between Return Loss       66 (1)
      and Impedance Matching
      3.2.3 Implementation of an Impedance         67 (1)
      Matching Network
    3.3 Impedance Matching Network Built by One    68 (6)
    Part
      3.3.1 One Part Inserted into Impedance       68 (2)
      Matching Network in Series
      3.3.2 One Part Inserted into the             70 (4)
      Impedance Matching Network in Parallel
    3.4 Impedance Matching Network Built by Two    74 (10)
    Parts
      3.4.1 Regions in a Smith Chart               74 (1)
      3.4.2 Values of Parts                        75 (6)
      3.4.3 Selection of Topology                  81 (3)
    3.5 Impedance Matching Network Built By        84 (1)
    Three Parts
      3.5.1 "Π" Type and "T" Type Topologies    84 (1)
      3.5.2 Recommended Topology                   84 (1)
    3.6 Impedance Matching When ZS Or ZL Is Not    85 (8)
    50 Ω
    3.7 Parts In An Impedance Matching Network     93 (1)
    Appendices                                     94 (30)
      3.A.1 Fundamentals of the Smith Chart        94 (5)
      3.A.2 Formula for Two-Part Impedance         99 (11)
      Matching Network
      3.A.3 Topology Limitations of the            110(4)
      Two-Part Impedance Matching Network
      3.A.4 Topology Limitation of Three Parts     114(8)
      Impedance Matching Network
      3.A.5 Conversion between Π and T Type     122(2)
      Matching Network
      3.A.6 Possible Π and T Impedance          124(1)
      Matching Networks
    Reference                                      124(1)
    Further Reading                                124(1)
    Exercises                                      125(2)
    Answers                                        127(4)
  4 Impedance Matching In The Wideband Case        131(50)
    4.1 Appearance of Narrow and Wideband          131(5)
    Return Loss on a Smith Chart
    4.2 Impedance Variation Due to the             136(9)
    Insertion of One Part Per Arm or Per Branch
      4.2.1 An Inductor Inserted into Impedance    137(2)
      Matching Network in Series
      4.2.2 A Capacitor Inserted into Impedance    139(2)
      Matching Network in Series
      4.2.3 An Inductor Inserted into Impedance    141(2)
      Matching Network in Parallel
      4.2.4 A Capacitor Inserted into Impedance    143(2)
      Matching Network in Parallel
    4.3 Impedance Variation Due to the             145(6)
    Insertion of Two Parts Per Arm or Per Branch
      4.3.1 Two Parts Connected in Series to       146(2)
      Form One Arm
      4.3.2 Two Parts Are Connected in Parallel    148(3)
      to Form One Branch
    4.4 Partial Impedance Matching for an IQ       151(23)
    (in Phase Quadrature) Modulator in a UWB
    (Ultra Wide Band) System
      4.4.1 Gilbert Cell                           151(2)
      4.4.2 Impedances of the Gilbert Cell         153(2)
      4.4.3 Impedance Matching for LO, RF, and     155(4)
      IF Ports Ignoring the Bandwidth
      4.4.4 Wide Bandwidth Required in a UWB       159(1)
      (Ultra Wide Band) System
      4.4.5 Basic Idea to Expand the Bandwidth     160(1)
      4.4.6 Example 1: Impedance Matching in IQ    161(11)
      Modulator Design for Group 1 in a UWB
      System
      4.4.7 Example 2: Impedance Matching in IQ    172(2)
      Modulator Design for Group 3 + Group 6 in
      a UWB System
    4.5 Discussion of Passive Wideband             174(5)
    Impedance Matching Network
      4.5.1 Impedance Matching for the Gate of     175(2)
      a MOSFET Device
      4.5.2 Impedance Matching for the Drain of    177(2)
      a MOSFET Device
    Further Reading                                179(1)
    Exercises                                      179(1)
    Answers                                        180(1)
  5 Impedance And Gain Of A Raw Device             181(78)
    5.1 Introduction                               181(2)
    5.2 Miller Effect                              183(4)
    5.3 Small-Signal Model of a Bipolar            187(3)
    Transistor
    5.4 Bipolar Transistor with CE (Common         190(14)
    Emitter) Configuration
      5.4.1 Open-Circuit Voltage Gain AvCE of a    190(4)
      CE Device
      5.4.2 Short-Circuit Current Gain βCE    194(2)
      and Frequency Response of a CE Device
      5.4.3 Primary Input and Output Impedance     196(1)
      of a CE (common emitter) device
      5.4.4 Miller's Effect in a Bipolar           197(3)
      Transistor with CE Configuration
      5.4.5 Emitter Degeneration                   200(4)
    5.5 Bipolar Transistor with CB (Common         204(10)
    Base) Configuration
      5.5.1 Open-Circuit Voltage Gain AvCB of a    204(2)
      CB Device
      5.5.2 Short-Circuit Current Gain βCG    206(2)
      and Frequency Response of a CB Device
      5.5.3 Input and Output Impedance of a CB     208(6)
      Device
    5.6 Bipolar Transistor with CC (Common         214(7)
    Collector) Configuration
      5.6.1 Open-Circuit Voltage Gain AvCC of a    214(3)
      CC Device
      5.6.2 Short-Circuit Current Gain βCG    217(1)
      and Frequency Response of the Bipolar
      Transistor with CC Configuration
      5.6.3 Input and Output Impedance of a CC     218(3)
      Device
    5.7 Small-Signal Model of a MOSFET             221(4)
    5.8 Similarity Between a Bipolar Transistor    225(10)
    and a MOSFET
      5.8.1 Simplified Model of CS Device          225(3)
      5.8.2 Simplified Model of CG Device          228(2)
      5.8.3 Simplified Model of CD Device          230(5)
    5.9 MOSFET with CS (Common Source)             235(9)
    Configuration
      5.9.1 Open-Circuit Voltage Gain AvCS of a    235(2)
      CS Device
      5.9.2 Short-Circuit Current Gain βCS    237(2)
      and Frequency Response of a CS Device
      5.9.3 Input and Output Impedance of a CS     239(1)
      Device
      5.9.4 Source Degeneration                    240(4)
    5.10 MOSFET with CG (Common Gate)              244(5)
    Configuration
      5.10.1 Open-Circuit Voltage Gain of a CG     244(1)
      Device
      5.10.2 Short-Circuit Current Gain and        245(2)
      Frequency Response of a CG Device
      5.10.3 Input and Output Impedance of a CG    247(2)
      Device
    5.11 MOSFET with CD (Common Drain)             249(3)
    Configuration
      5.11.1 Open-Circuit Voltage Gain AvCD of     250(1)
      a CD Device
      5.11.2 Short-Circuit Current Gain            250(1)
      βCD and Frequency Response of a CD
      Device
      5.11.3 Input and Output Impedance of a CD    251(1)
      Device
    5.12 Comparison of Transistor Configuration    252(4)
    of Single-stage Amplifiers with Different
    Configurations
    Further Reading                                256(1)
    Exercises                                      256(1)
    Answers                                        256(3)
  6 Impedance Measurement                          259(22)
    6.1 Introduction                               259(1)
    6.2 Scalar and Vector Voltage Measurement      260(3)
      6.2.1 Voltage Measurement by Oscilloscope    260(2)
      6.2.2 Voltage Measurement by Vector          262(1)
      Voltmeter
    6.3 Direct Impedance Measurement by a          263(9)
    Network Analyzer
      6.3.1 Direction of Impedance Measurement     263(2)
      6.3.2 Advantage of Measuring S Parameters    265(1)
      6.3.3 Theoretical Background of Impedance    266(2)
      Measurement by S Parameters
      6.3.4 S Parameter Measurement by Vector      268(2)
      Voltmeter
      6.3.5 Calibration of the Network Analyzer    270(2)
    6.4 Alternative Impedance Measurement by       272(4)
    Network Analyzer
      6.4.1 Accuracy of the Smith Chart            272(3)
      6.4.2 Low- and High-Impedance Measurement    275(1)
    6.5 Impedance Measurement Using a Circulator   276(1)
    Appendices                                     277(1)
      6.A.1 Relationship Between the Impedance     277(1)
      in Series and in Parallel
    Further Reading                                278(1)
    Exercises                                      278(1)
    Answers                                        279(2)
  7 Grounding                                      281(44)
    7.1 Implication of Grounding                   281(2)
    7.2 Possible Grounding Problems Hidden in a    283(1)
    Schematic
    7.3 Imperfect or Inappropriate Grounding       284(6)
    Examples
      7.3.1 Inappropriate Selection of Bypass      284(2)
      Capacitor
      7.3.2 Imperfect Grounding                    286(2)
      7.3.3 Improper Connection                    288(2)
    7.4 'Zero' Capacitor                           290(10)
      7.4.1 What is a Zero Capacitor               290(1)
      7.4.2 Selection of a Zero Capacitor          290(3)
      7.4.3 Bandwidth of a Zero Capacitor          293(2)
      7.4.4 Combined Effect of Multi-Zero          295(1)
      Capacitors
      7.4.5 Chip Inductor is a Good Assistant      296(2)
      7.4.6 Zero Capacitor in RFIC Design          298(2)
    7.5 Quarter Wavelength of Microstrip Line      300(9)
      7.5.1 A Runner is a Part in RF Circuitry     300(4)
      7.5.2 Why Quarter Wavelength is so           304(1)
      Important
      7.5.3 Magic Open-Circuited Quarter           305(2)
      Wavelength of Microstrip Line
      7.5.4 Testing for Width of Microstrip        307(1)
      Line with Specific Characteristic
      Impedance
      7.5.5 Testing for Quarter Wavelength         307(2)
    Appendices                                     309(12)
      7.A.1 Characterizing of Chip Capacitor       309(10)
      and Chip Inductor by Means of S21 Testing
      7.A.2 Characterizing of Chip Resistor by     319(2)
      Means of S11 of S22 Testing
    Reference                                      321(1)
    Further Reading                                322(1)
    Exercises                                      322(1)
    Answers                                        323(2)
  8 Equipotentiality And Current Coupling On       325(24)
  The Ground Surface
    8.1 Equipotentiality on the Ground Surface     325(10)
      8.1.1 Equipotentiality on the Grounded       325(1)
      Surface of an RF Cable
      8.1.2 Equipotentiality on the Grounded       326(1)
      Surface of a PCB
      8.1.3 Possible Problems of a Large Test      327(1)
      PCB
      8.1.4 Coercing Grounding                     328(5)
      8.1.5 Testing for Equipotentiality           333(2)
    8.2 Forward and Return Current Coupling        335(9)
      8.2.1 Indifferent Assumption and Great       335(1)
      Ignore
      8.2.2 Reduction of Current Coupling on a     336(2)
      PCB
      8.2.3 Reduction of Current Coupling in an    338(2)
      IC Die
      8.2.4 Reduction of Current Coupling          340(1)
      between Multiple RF Blocks
      8.2.5 A Plausible System Assembly            341(3)
    8.3 PCB or IC Chip with Multimetallic Layers   344(2)
    Further Reading                                346(1)
    Exercises                                      346(1)
    Answers                                        347(2)
  9 Layout                                         349(28)
    9.1 Difference in Layout between an            349(1)
    Individual Block and a System
    9.2 Primary Considerations of a PCB            350(2)
      9.2.1 Types of PCBs                          350(1)
      9.2.2 Main Electromagnetic Parameters        351(1)
      9.2.3 Size                                   351(1)
      9.2.4 Number of Metallic Layers              352(1)
    9.3 Layout of a PCB for Testing                352(3)
    9.4 VIA Modeling                               355(5)
      9.4.1 Single Via                             355(4)
      9.4.2 Multivias                              359(1)
    9.5 Runner                                     360(9)
      9.5.1 When a Runner is Connected with the    360(3)
      Load in Series
      9.5.2 When a Runner is Connected to the      363(1)
      Load in Parallel
      9.5.3 Style of Runner                        363(6)
    9.6 Parts                                      369(2)
      9.6.1 Device                                 369(1)
      9.6.2 Inductor                               369(1)
      9.6.3 Resistor                               370(1)
      9.6.4 Capacitor                              370(1)
    9.7 Free Space                                 371(2)
    References                                     373(1)
    Further Reading                                373(1)
    Exercises                                      373(1)
    Answers                                        374(3)
  10 Manufacturability Of Product Design           377(24)
    10.1 Introduction                              377(2)
    10.2 Implication of 6σ Design            379(4)
      10.2.1 6σ and Yield Rate               379(3)
      10.2.2 6σ Design for a Circuit Block   382(1)
      10.2.3 6σ Design for a Circuit         383(1)
      System
    10.3 Approaching 6σ Design               383(3)
      10.3.1 By Changing of Parts' σ Value   383(2)
      10.3.2 By Replacing Single Part with         385(1)
      Multiple Parts
    10.4 Monte Carlo Analysis                      386(6)
      10.4.1 A Band-Pass Filter                    386(1)
      10.4.2 Simulation with Monte Carlo           387(5)
      Analysis
      10.4.3 Sensitivity of Parts on the           392(1)
      Parameter of Performance
    Appendices                                     392(6)
      10.A.1 Fundamentals of Random Process        392(6)
      10.A.2 Index Cp and Cpk Applied in           398(1)
      6σ Design
      10.A.3 Table of the Normal Distribution      398(1)
    Further Reading                                398(1)
    Exercises                                      399(1)
    Answers                                        399(2)
  11 RFIC (Radio Frequency Integrated Circuit)     401(26)
    11.1 Interference and Isolation                401(2)
      11.1.1 Existence of Interference in          401(1)
      Circuitry
      11.1.2 Definition and Measurement of         402(1)
      Isolation
      11.1.3 Main Path of Interference in a RF     403(1)
      Module
      11.1.4 Main Path of Interference in an IC    403(1)
      Die
    11.2 Shielding for an RF Module by a           403(2)
    Metallic Shielding Box
    11.3 Strong Desirability to Develop RFIC       405(1)
    11.4 Interference going along IC Substrate     406(5)
    Path
      11.4.1 Experiment                            406(2)
      11.4.2 Trench                                408(1)
      11.4.3 Guard Ring                            409(2)
    11.5 Solution for Interference Coming from     411(1)
    Sky
    11.6 Common Grounding Rules for RF Module      412(2)
    and RFIC Design
      11.6.1 Grounding of Circuit Branches or      412(1)
      Blocks in Parallel
      11.6.2 DC Power Supply to Circuit            413(1)
      Branches or Blocks in Parallel
    11.7 Bottlenecks in RFIC Design                414(6)
      11.7.1 Low-Q Inductor and Possible           414(5)
      Solution
      11.7.2 "Zero" Capacitor                      419(1)
      11.7.3 Bonding Wire                          419(1)
      11.7.4 Via                                   419(1)
    11.8 Calculating of Quarter Wavelength         420(3)
    Reference                                      423(1)
    Further Reading                                423(1)
    Exercises                                      424(1)
    Answers                                        425(2)
Part 2 RF System                                   427(198)
  12 Main Parameters And System Analysis In RF     429(72)
  Circuit Design
    12.1 Introduction                              429(2)
    12.2 Power Gain                                431(10)
      12.2.1 Basic Concept of Reflection Power     431(3)
      Gain
      12.2.2 Transducer Power Gain                 434(3)
      12.2.3 Power Gain in a Unilateral Case       437(1)
      12.2.4 Power Gain in a Unilateral and        438(1)
      Impedance-Matched Case
      12.2.5 Power Gain and Voltage Gain           439(1)
      12.2.6 Cascaded Equations of Power Gain      439(2)
    12.3 Noise                                     441(12)
      12.3.1 Significance of Noise Figure          441(2)
      12.3.2 Noise Figure in a Noisy Two-Port      443(1)
      RF Block
      12.3.3 Notes on Noise Figure Testing         444(1)
      12.3.4 An Experimental Method to Obtain      445(1)
      Noise Parameters
      12.3.5 Cascaded Equations of Noise Figure    446(2)
      12.3.6 Sensitivity of a Receiver             448(5)
    12.4 Nonlinearity                              453(27)
      12.4.1 Nonlinearity of a Device              453(8)
      12.4.2 IP (Intercept Point) and IMR          461(11)
      (Intermodulation Rejection)
      12.4.3 Cascaded Equations of Intercept       472(7)
      Point
      12.4.4 Nonlinearity and Distortion           479(1)
    12.5 Other Parameters                          480(2)
      12.5.1 Power Supply Voltage and Current      480(2)
      Drain
      12.5.2 Part Count                            482(1)
    12.6 Example of RF System Analysis             482(3)
    Appendices                                     485(6)
      12.A.1 Conversion between Watts, Volts,      485(1)
      and dBm, in a System with 50 Ω
      Input and Output Impedance
      12.A.2 Relationship between voltage          485(3)
      reflection coefficient, Γ, and
      Transmission coefficients when the load
      R　is equal to the standard
      characteristic resistance, 50 Ω)
      12.A.3 Definition of Powers in a Two-Port    488(1)
      Block by Signal Flow Graph
      12.A.4 Main Noise Sources                    489(2)
    References                                     491(1)
    Further Reading                                491(2)
    Exercises                                      493(1)
    Answers                                        494(7)
  13 Speciality of "Zero If" System                501(20)
    13.1 Why Differential Pair?                    501(7)
      13.1.1 Superficial Difference between        501(2)
      Single-Ended and Differential Pair
      13.1.2 Nonlinearity in Single-Ended Stage    503(2)
      13.1.3 Nonlinearity in a Differential Pair   505(2)
      13.1.4 Importance of Differential            507(1)
      Configuration in a Direct Conversion or
      Zero IF Communication System
      13.1.5 Why Direct Conversion or Zero IF?     508(1)
    13.2 Can DC Offset be Blocked out by a         508(3)
    Capacitor?
    13.3 Chopping Mixer                            511(5)
    13.4 DC Offset Cancellation by Calibration     516(1)
    13.5 Remark on DC Offset Cancellation          517(1)
    Further Reading                                517(1)
    Exercises                                      518(1)
    Answers                                        519(2)
  14 Differential Pairs                            521(26)
    14.1 Fundamentals of Differential Pairs        521(12)
      14.1.1 Topology and Definition of a          521(3)
      Differential Pair
      14.1.2 Transfer Characteristic of a          524(3)
      Bipolar Differential Pair
      14.1.3 Small Signal Approximation of a       527(1)
      Bipolar Differential Pair
      14.1.4 Transfer Characteristic of a          528(2)
      MOSFET Differential Pair
      14.1.5 Small Signal Approximation of a       530(1)
      MOSFET Differential Pair
      14.1.6 What Happens If Input Signal Is       531(2)
      Imperfect Differential
    14.2 CMRR (Common Mode Rejection Ratio)        533(9)
      14.2.1 Expression of CMRR                    533(6)
      14.2.2 CMRR in a Single-Ended Stage          539(1)
      14.2.3 CMRR in a Pseudo-Differential Pair    539(2)
      14.2.4 Enhancement of CMRR                   541(1)
    Reference                                      542(1)
    Further Reading                                542(1)
    Exercises                                      542(1)
    Answers                                        543(4)
  15 RF Balun                                      547(64)
    15.1 Introduction                              547(2)
    15.2 Transformer Balun                         549(22)
      15.2.1 Transformer Balun in RF Circuit       550(1)
      Design with Discrete Parts
      15.2.2 Transformer Balun in RFIC Design      550(1)
      15.2.3 An Ideal Transformer Balun for        551(4)
      Simulation
      15.2.4 Equivalence of Parts between          555(13)
      Single-Ended and Differential Pair in
      Respect to an Ideal Transformer Balun
      15.2.5 Impedance Matching for                568(3)
      Differential Pair by means of Transformer
      Balun
    15.3 LC Balun                                  571(9)
      15.3.1 Simplicity of LC Balun Design         572(1)
      15.3.2 Performance of a Simple LC Balun      572(4)
      15.3.3 A Practical LC Balun                  576(4)
    15.4 Microstrip Line Balun                     580(3)
      15.4.1 Ring Balun                            580(2)
      15.4.2 Split Ring Balun                      582(1)
    15.5 Mixing Type of Balun                      583(3)
      15.5.1 Balun Built by Microstrip Line and    583(2)
      Chip Capacitor
      15.5.2 Balun Built by Chip Inductors and     585(1)
      Chip Capacitors
    Appendices                                     586(18)
      15.A.1 Transformer Balun Built by Two        586(2)
      Stacked Transformers
      15.A.2 Analysis of a Simple LC Balun         588(4)
      15.A.3 Example of Calculating of L and C     592(1)
      Values for a Simple LC Balun
      15.A.4 Equivalence of Parts between          592(10)
      Single-Ended and Differential Pair with
      Respect to a Simple LC Balun
      15.A.5 Some Useful Couplers                  602(1)
      15.A.6 Cable Balun                           603(1)
    Reference                                      604(1)
    Further Reading                                604(1)
    Exercises                                      605(1)
    Answers                                        606(5)
  16 SOC (System-On-A-Chip) And Next               611(14)
    16.1 SOC                                       611(1)
      16.1.1 Basic Concept                         611(1)
      16.1.2 Remove Bottlenecks in Approach to     612(1)
      RFIC
      16.1.3 Study Isolation between RFIC,         612(1)
      Digital IC, and Analog IC
    16.2 What is Next                              612(3)
    Appendices                                     615(6)
      16.A.1 Packaging                             615(6)
    References                                     621(1)
    Further Reading                                622(1)
    Exercises                                      622(1)
    Answers                                        623(2)
Part 3 Individual RF Blocks                        625(208)
  17 LNA (Low-Noise Amplifier)                     627(68)
    17.1 Introduction                              627(1)
    17.2 Single-Ended Single Device LNA            628(34)
      17.2.1 Size of Device                        629(3)
      17.2.2 Raw Device Setup and Testing          632(7)
      17.2.3 Challenge for a Good LNA Design       639(7)
      17.2.4 Input and Output Impedance Matching   646(2)
      17.2.5 Gain Circles and Noise Figure         648(1)
      Circles
      17.2.6 Stability                             649(4)
      17.2.7 Nonlinearity                          653(2)
      17.2.8 Design Procedures                     655(1)
      17.2.9 Other Examples                        656(6)
    17.3 Single-Ended Cascode LNA                  662(22)
      17.3.1 Bipolar CE-CB Cascode Voltage         662(4)
      Amplifier
      17.3.2 MOSFET CS-CG Cascode Voltage          666(3)
      Amplifier
      17.3.3 Why Cascode?                          669(2)
      17.3.4 Example                               671(13)
    17.4 LNA with AGC (Automatic Gain Control)     684(6)
      17.4.1 AGC Operation                         684(2)
      17.4.2 Traditional LNA with AGC              686(2)
      17.4.3 Increase in AGC Dynamic Range         688(1)
      17.4.4 Example                               689(1)
    References                                     690(1)
    Further Reading                                690(1)
    Exercises                                      691(1)
    Answers                                        692(3)
  18 Mixer                                         695(36)
    18.1 Introduction                              695(3)
    18.2 Passive Mixer                             698(8)
      18.2.1 Simplest Passive Mixer                698(1)
      18.2.2 Double-Balanced Quad-Diode Mixer      699(3)
      18.2.3 Double-Balanced Resistive Mixer       702(4)
    18.3 Active Mixer                              706(11)
      18.3.1 Single-End Single Device Active       706(2)
      Mixer
      18.3.2 Gilbert Cell                          708(4)
      18.3.3 Active Mixer with Bipolar Gilbert     712(3)
      Cell
      18.3.4 Active Mixer with MOSFET Gilbert      715(2)
      Cell
    18.4 Design Schemes                            717(6)
      18.4.1 Impedance Measuring and Matching      717(1)
      18.4.2 Current Bleeding                      718(1)
      18.4.3 Multi-tanh Technique                  719(3)
      18.4.4 Input Types                           722(1)
    Appendices                                     723(3)
      18.A.1 Trigonometric and Hyperbolic          723(1)
      Functions
      18.A.2 Implementation of tanh-ｹ Block        724(2)
    References                                     726(1)
    Further Reading                                726(1)
    Exercises                                      726(1)
    Answers                                        727(4)
  19 Tunable Filter                                731(18)
    19.1 Tunable Filter in A Communication         731(2)
    System
      19.1.1 Expected Constant Bandwidth of a      732(1)
      Tunable Filter
      19.1.2 Variation of Bandwidth                732(1)
    19.2 Coupling between two Tank Circuits        733(5)
      19.2.1 Inappropriate Coupling                735(3)
      19.2.2 Reasonable Coupling                   738(1)
    19.3 Circuit Description                       738(1)
    19.4 Effect of Second Coupling                 739(4)
    19.5 Performance                               743(3)
    Further Reading                                746(1)
    Exercises                                      747(1)
    Answers                                        747(2)
  20 VCO (Voltage-Controlled Oscillator)           749(40)
    20.1 "Three-Point" Types of Oscillator         749(6)
      20.1.1 Hartley Oscillator                    751(2)
      20.1.2 Colpitts Oscillator                   753(1)
      20.1.3 Clapp Oscillator                      753(2)
    20.2 Other Single-Ended Oscillators            755(4)
      20.2.1 Phase-Shift Oscillator                755(2)
      20.2.2 TITO (Tuned Input and Tuned           757(1)
      Output) Oscillator
      20.2.3 Resonant Oscillator                   757(1)
      20.2.4 Crystal Oscillator                    758(1)
    20.3 VCO and PLL (Phase Lock Loop)             759(10)
      20.3.1 Implication of VCO                    759(1)
      20.3.2 Transfer Function of PLL              760(3)
      20.3.3 White Noise from the Input of the     763(1)
      PLL
      20.3.4 Phase Noise from a VCO                764(5)
    20.4 Design Example of a Single-Ended VCO      769(9)
      20.4.1 Single-Ended VCO with Clapp           769(1)
      Configuration
      20.4.2 Varactor                              770(1)
      20.4.3 Printed Inductor                      770(3)
      20.4.4 Simulation                            773(3)
      20.4.5 Load-Pulling Test and VCO Buffer      776(2)
    20.5 Differential VCO and Quad-Phases VCO      778(5)
    Reference                                      783(1)
    Further Reading                                783(1)
    Exercises                                      784(1)
    Answers                                        784(5)
  21 PA (Power Amplifier)                          789(44)
    21.1 Classification of PA                      789(5)
      21.1.1 Class A Power Amplifier               790(1)
      21.1.2 Class B Power Amplifier               790(1)
      21.1.3 Class C Power Amplifier               791(1)
      21.1.4 Class D Power Amplifier               791(1)
      21.1.5 Class E Power Amplifier               792(1)
      21.1.6 Third-Harmonic-Peaking Class F        793(1)
      Power Amplifier
      21.1.7 Class S Power Amplifier               794(1)
    21.2 Single-Ended PA                           794(4)
      21.2.1 Taming on the Bench                   795(1)
      21.2.2 Simulation                            796(2)
    21.3 Single-Ended PA IC Design                 798(1)
    21.4 Push-Pull PA Design                       799(23)
      21.4.1 Main Specification                    799(1)
      21.4.2 Block Diagram                         799(1)
      21.4.3 Impedance Matching                    800(4)
      21.4.4 Reducing the Block Size               804(4)
      21.4.5 Double Microstrip Line Balun          808(9)
      21.4.6 Toroidal RF Transformer Balun         817(5)
    21.5 PA with Temperature Compensation          822(1)
    21.6 PA with Output Power Control              823(1)
    21.7 Linear PA                                 824(4)
    References                                     828(1)
    Further Reading                                828(1)
    Exercises                                      829(1)
    Answers                                        829(4)
Index                                              833