LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY decl7s IS
PORT(
d: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --输入4位二进制码
seg: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) --七段译码输出
);
END;
ARCHITECTURE ONE OF decl7s IS
SIGNAL seg_r:STD_LOGIC_VECTOR(7 DOWNTO 0); --定义数码管输出寄存器
BEGIN
seg<=seg_r; --输出数码管译码结果
PROCESS(d) --七段译码
BEGIN
CASE d IS
WHEN X"0"=> seg_r<=X"c0";--显示0
WHEN X"1"=> seg_r<=X"f9";--显示1
WHEN X"2"=> seg_r<=X"a4";--显示2
WHEN X"3"=> seg_r<=X"b0";--显示3
WHEN X"4"=> seg_r<=X"99";--显示4
WHEN X"5"=> seg_r<=X"92";--显示5
WHEN X"6"=> seg_r<=X"82";--显示6
WHEN X"7"=> seg_r<=X"f8";--显示7
WHEN X"8"=> seg_r<=X"80";--显示8
WHEN X"9"=> seg_r<=X"90";--显示9
WHEN X"a"=> seg_r<=X"88";--显示a
WHEN X"b"=> seg_r<=X"83";--显示b
WHEN X"c"=> seg_r<=X"c6";--显示c
WHEN X"d"=> seg_r<=X"a1";--显示d
WHEN X"e"=> seg_r<=X"86";--显示e
WHEN X"f"=> seg_r<=X"8e";--显示f
WHEN OTHERS=> seg_r<=X"FF";
END CASE;
END PROCESS;
END;