First Author: Q. Wang

Correspondence Author: G. Yu*

Co-author: A. Hu, D. Han, Y. Yu, Y. Li and C. Wang

Journal: IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia 2022)

Included Journals: EI

Discipline: Engineering

First-Level Discipline: Electronic Science And Technology

Document Type: C

Date of Publication: 2022-10-03

Abstract: Simultaneous localization and mapping (SLAM) is the major solution for constructing or updating a map of an unknown environment while simultaneously keeping track of a mobile robot's location. Correlative Scan Matching (CSM) is a scan matching algorithm for obtaining the posterior distribution probability for the robot's pose in SLAM. This paper presents a hardware accelerator design of NLO-CSM (Non-linear Optimization CSM) algorithm for the scan matching in 2D LiDAR SLAM. The proposed NLO-CSM algorithm hardware accelerator utilizes pipeline processing and module reusing to achieve low power consumption, fast matching and high area efficiency, while ensuring high calculation accuracy. FPGA implementation results show that at 100 MHz clock, the power consumption of the proposed hardware accelerator is as low as 139 mW, while it performs a scan matching at 34.8 ms and 4.837 mJ. The proposed design outperforms the conventional CPU implementation with 69.44% increase and 93.17% saving in computing speed and energy consumption, respectively. ASIC implementation in 65 nm can further improve the energy efficiency by 93.05%, by reducing the computing time and energy consumption per scan to 30 ms and 0.336 mJ, respectively, which shows that the proposed NLO-CSM hardware accelerator design is suitable for resource-limited and energy-constrained mobile and micro robot applications.