REN: A Reconfigurable End-to-end NeuroSLAM Hardware Accelerator for Micro Mobile Robots

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First Author:Zixuan Shen, Jian Xiao

Correspondence Author:C. Wang*

Co-author:H. Peng, Y. Mei, B. Shi, Z. Wei, B. Dong, Y. Zheng, and

Journal:2025 IEEE International Symposium on Artificial Intelligence Circuits and Systems (AICAS 2025)

Included Journals:EI

Discipline:Engineering

First-Level Discipline:Electronic Science And Technology

Document Type:C

Abstract:Visual Simultaneous Localization and Mapping (VSLAM) is essential for enabling autonomous systems to navigate in unknown environments. Brain-inspired VSLAM algorithms are valued for their energy efficiency and robustness. Inspired by the hippocampal mechanisms in rodents, this paper proposes a Reconfigurable End-to-end NeuroSLAM (REN) accelerator for micro mobile robots. The proposed end-to-end hardware architecture, with a novel Dynamic Reconfigurable Dual-mode-PE Cluster (DR-DPC), is employed to fully accelerate the NeuroSLAM algorithm to reduce energy consumption and processing latency. The DR-DPC with 8 PE groups is proposed to accelerate the three major tasks of the NeuroSLAM, to save hardware overhead and achieve high hardware utilization. A Dynamic PE-group Allocation Scheme (DPAS) for the DR-DPC is used to efficiently allocate the PE groups to balance the latency of visual odometry and loop closure detection tasks to improve hardware utilization, reduce the process latency and improve energy efficiency. FPGA hardware implementation results exhibit that the proposed REN accelerator design can achieve a high energy efficiency of 67.1 GOPS/W, a PE utilization of ~85% in average, and a frame rate of 90 fps@VGA, among the state-of-the-art designs.